Manufacturability-aware physical integrated circuit (IC) design processes, which take into account such factors as yield and reliability, are becoming increasingly important aspects in bridging the gap between what is designed and what is actually produced or fabricated. This disconnect between design and production is often attributable to physical layout patterns (or configurations), also referred to herein as problematic layout patterns, being susceptible to various processing issues related to the manufacturing processes being employed. For instance, ICs are often fabricated using one or more deposition-based, modification-based (e.g., doping, implantation, etc.), patterning-based (e.g., lithography), removal-based (e.g., etching, planarization, etc.), and the like processing steps prone to various processing fluctuations, such as bridging, necking, notching, pinching, stressing, and the like issues, as well as other parametric design marginalities. These manufacturing issues are often the result of attempts to fabricate at least one problematic layout pattern. It is, therefore, desirable to be able to identity and remove these problematic layout patterns, as well as to replace them with more reliable, yield-friendly configurations.
Traditionally, physical IC design verification has focused primarily on design verification rules-based approaches. For example, design rule checking (DRC) is an area of electronic design automation (EDA) that enables IC designers to determine whether a particular physical layout design satisfies a series of parameters, also referred to as design rules. Design rules are typically provided by IC manufacturers (e.g., foundries) to enable IC designers to verify the “correctness” of their physical layout patterns. In this manner, design rules are often associated with specific manufacturing processes. Thus, a set of design rules may specify certain IC feature (e.g., geometric element) and/or connectivity restrictions to ensure sufficient margins are present to account for the variability in one or more manufacturing processes. As such, design rule checking is a major step during physical verification of physical IC layout configurations, which may also involve one or more antenna checks, electrical rule checks (ERC), exclusive or (XOR) checks, layout versus schematic (LVS) checks, etc.
As the demand for increased feature densities grows and manufacturing processes evolve, design rule sets are becoming increasingly more complex. Accordingly, one objective of design verification is to achieve a certain level of yield and reliability for a particular physical IC layout pattern. If design rules are violated the design may not be functional. To meet this goal of improving yield and/or reliability, design verification has evolved from simple measurement and Boolean check-based techniques to processes that modify existing features, insert new features, and check entire designs for process limitations. A completed layout consists not only of the geometric representation of the design itself, but also data that provides support for manufacturing the design. While design verification processes do not necessarily ensure a particular physical IC layout pattern will operate correctly, these processes are constructed to at least verify that the physical configuration meets certain processing constraints for given design types and/or manufacturing process technologies. As such, design verification tools usually receive physical IC layout patterns (or designs) in one or more standardized formats, and produce results (e.g., reports) of any design verification violations that an IC designer may or may not choose to correct based on the application of one or more design verification rules against the received designs. Strategically waiving certain design verification rules is often utilized to increase IC performance and density, but generally at the expense of yield and/or reliability.
Thus, as physical IC layout patterns become more complex, the execution of design verification techniques is becoming evermore computationally intensive. For instance, some design verification techniques, if executed on a single processing platform, may require several days (if not weeks) to generate results. In competitive environments like the semiconductor industry, however, design cycles need to be as short as possible; lengthy design verification processes only burden such efforts.
Moreover, satisfaction of one particular set of design verification rules may not be adequate when the design verification rules are affected by the complexity of the layout pattern containing a particular feature or rule. One particular design verification rule may be adequate for certain particular physical IC layout patterns, but may require modification when applied against another physical IC layout pattern. For example, DRC processes may be performed by checking the physical properties of one or more “as-designed” geometric elements included as part of a physical IC layout pattern (or design) against one or more permissible design verification rules, such as rules regarding area, grid, length, size, spacing, corner, enclosure, intersection, overlap, and/or the like. As such, DRC is becoming the industry standard for constraining designs to ensure adequate physical and electrical manufacturability. However, as technology processes continue to shrink and aggressive resolution enhancement technologies (RET), optical proximity corrections (OPC), laser trimming, and/or other corrective manufacturing processes are applied, physical IC layout patterns verified by conventional verification techniques may still be difficult to manufacture. There have been attempts to resolve the inconsistencies of conventional design verification approaches, such as through the application of additional rules to identify specific problematic cases, but due to the lack of specificity with design verification itself, these efforts have been met with mixed-success. Even though these alternative approaches may resolve existing issues, often, the enforcement of some design verification rules causes other problematic layout patterns to occur as IC designers attempt to satisfy all the constraints imposed upon their designs.
Design verification plus, such as DRC-Plus, adopts a different approach to rectifying the inconsistencies of conventional DRC approaches. For instance, DRC-Plus may augment conventional design verification approaches with one or more multi-dimensional pattern matching techniques capable of identifying problematic layout patterns predetermined to be difficult to manufacture. In this manner, design verification plus tools may also be configured to return specific feedback to IC designers on how to resolve one or more identified issues. This approach offers several advantages over other manufacturability-aware techniques, such as being quickly and efficiently enforceable and providing pass/no-pass criteria. It also provides simple documentation within design manuals, it is not as computationally intensive as rules-based or simulation-based approaches, and it does not require highly-accurate manufacturability models, such as lithographic or other manufacturing-based models, that may not be available during design verification processes. These advantages enable design verification plus approaches to be applied early in the design flow, as well as enforced in conjunction with other conventional design verification techniques, if desired.
Another issue as physical IC layout patterns become more complex involves the increased reliance on “off-the-shelf” physical IC block layout patterns (hereinafter referred to as physical block designs) that are preconfigured to achieve one or more particular purposes. While these physical block designs are, in effect, being utilized as modular components capable of integration as part of other IC designs, such as full system on chip (SoC) designs, the routing and placement of these modular components is proving to be difficult. Since these physical block designs may be randomly placed and routed in juxtaposition with one or more other physical IC layout patterns, the risk of creating at least one problematic layout pattern increases once one or more geometric elements of a modular physical block design are randomly placed and routed in relative proximity to one or more other geometric elements of another IC design. This creates a gap between the time when the physical block is designed and the time when the physical block design is incorporated as part of another design. Conventional design verification and design verification plus approaches, however, act upon actually present physical layout patterns and, therefore, are unable to predict, identify, and handle “potentially” problematic layout patterns included as part of a physical block design that may result in “actual” problematic layout patterns once the physical block design is integrated as part of another IC design.
A need, therefore, exists for methodology enabling efficient, preemptive design verification tools capable of identifying and handling potentially problematic layout patterns that may result in actual problematic layout patterns once a physical block design is incorporated as part of another IC design, such as a full SoC design. There exists a particular need for methodology enabling identification of potentially problematic layout patterns via multi-dimensional pattern matching technology.